#include <config.h>
#include <arch/arm.h>
#include <arch/cpu/soc/mach/setup.h>

.global _start
_start:
	b reset_handler
	b undef_handler
	b swi_handler
	b iabort_handler
	b dabort_handler
	b hang
	b irq_handler
	b fiq_handler

reset_handler:
    /* set the cpu to SVC32 mode and disable IRQ FIQ */
    msr cpsr_c, #(ARM_MODE_SVC | ARM_INT_MASK)

	MACHINE_SETUP

clear_bss:
	ldr r0, =__bss_start
	ldr r1, =__bss_end
	mov r2, #0
clbss_l:
	cmp r0, r1
	strne r2, [r0]
	addne r0, r0, #4
	bne clbss_l
	
	ldr r0, =__bss_end
	add r0, r0, #CONFIG_TH_STACK_SIZE
	mov sp, r0

    b board_init

undef_handler:
swi_handler:
iabort_handler:
dabort_handler:
irq_handler:
fiq_handler:
hang:
	b hang

